October, 2015

CMPEN 270 has taught me basic Verilog skills to program an Altera FPGA. The code below forms a 4 bit adder with overflow detection.

//Top level code

module Adder4bit_Display(
    input [3:0] NUM1, NUM2,
    output Overflow,
    output [7:0] Display_NUM1, Display_NUM2, Display_SUM
);
wire [3:0]wsum;
wire wcout;

fourBitAdder adderdude(NUM1,NUM2,0,wsum,wcout);

assign Overflow = ~((wsum[3]^wcout) & (~(NUM1[3]^NUM2[3])));

Binary2Eight num1dude(NUM1,Display_NUM1);
Binary2Eight num2dude (NUM2,Display_NUM2);
Binary2Eight sumdude (wsum, Display_SUM);

endmodule

//Adder modlue formed from 4 full adders

module fourBitAdder (X,Y,CinFour,SumFour,CoutFour);//Make a 4-bit Adder module here using TwobitAdder below.
    input [3:0] X;
    input [3:0] Y;
    input CinFour;
    output [3:0] SumFour;
    output CoutFour;
    
    wire Carry1, Carry2, Carry3;
    
    Add_full_0_delay ripple1(SumFour[0],Carry1,X[0],Y[0],CinFour);
    Add_full_0_delay ripple2(SumFour[1],Carry2,X[1],Y[1],Carry1);
    Add_full_0_delay ripple3(SumFour[2],Carry3,X[2],Y[2],Carry2);
    Add_full_0_delay ripple4(SumFour[3],CoutFour,X[3],Y[3],Carry3);
endmodule

module Add_full_0_delay(sum,c_out,a,b,c_in);    
    output sum,c_out;
    input a,b,c_in;
    wire w1,w2,w3;
    
    Add_half_0_delay M1(w1,w2,a,b);
    Add_half_0_delay M2(sum,w3,c_in,w1);
    or               M3(c_out,w2,w3);
endmodule

module Add_half_0_delay(sum,c_out,a,b);    
    output sum,c_out;
    input  a,b;
    
    xor    M1(sum,a,b);
    and    M2(c_out,a,b);    
endmodule

//Display decoding

module Binary2Eight(
    input [3:0] Num,
    output reg [7:0] SevenSeg
);

always@(*)
begin
  case(Num)
     4'b0000: SevenSeg = 8'b11000000;         //0
     4'b0001: SevenSeg = 8'b11111001;          //1
     4'b0010: SevenSeg = 8'b10100100;            //2
     4'b0011: SevenSeg = 8'b10110000;            //3
     4'b0100: SevenSeg = 8'b10011001;            //4
     4'b0101: SevenSeg = 8'b10010010;            //5
     4'b0110: SevenSeg = 8'b10000010;             //6
     4'b0111: SevenSeg = 8'b11111000;            //7
    
     4'b1000: SevenSeg = 8'b00000000;         //-8
     4'b1001: SevenSeg = 8'b01111000;            //-7
     4'b1010: SevenSeg = 8'b00000010;            //-6
     4'b1011: SevenSeg = 8'b00010010;            //-5
     4'b1100: SevenSeg = 8'b00011001;            //-4
     4'b1101: SevenSeg = 8'b00110000;            //-3
     4'b1110: SevenSeg = 8'b00100100;            //-2
     4'b1111: SevenSeg = 8'b01111001;            //-1
    endcase
end
endmodule